1. Field of the Invention
This invention relates to an MOS-type integrated circuit structure, and a method of making same, wherein one or more diodes are formed in a semiconductor substrate beneath the polysilicon gate electrode of an MOS-type integrated circuit structure. The one or more diodes are provided to reduce plasma damage to and charging of the gate oxide, thus improving the overall reliability of the product. The location of the one or more diodes beneath the polysilicon gate electrode serves to conserve space on the substrate, and thus, reduces the cost of the product.
2. Description of the Related Art
Advances in MOS technology, including reduction in scale, have resulted in the reduction of the gate oxide thickness to thinner and thinner values. This reduction in gate oxide thicknesses and the increased use of plasma technology, particularly starting at the first interconnect level, has generated increasing demands on a thinner dielectric. More specifically, plasma processing has been demonstrated to cause damage to the quality of the gate oxide. This damage occurs because high frequency RF signals are applied to the structure, including the gate oxide, during many steps in the process of forming an MOS-type integrated circuit structure. Examples of plasma steps which can result in exposure of the gate oxide to such high frequency RF signals include, for example, plasma stripping of photoresist, pre-metal deposition sputter etching, etchback of tungsten used to fill vias and contact openings, and patterning of metallization layers by etching.
The high frequency RF signals generated during such processing induce AC currents which pass through the gate oxide leaving small mounts of charge trapped in the oxide with each pass of the field. Such processing then reduces the overall reliability of the oxide, thereby increasing the possibility of failure of the integrated circuit structure during use.
It has been proposed to reduce such damage to the gate oxide by AC currents induced by the high frequency RF signals from plasma processing, using a diode electrically connected between the gate electrode and the substrate. This is illustrated schematically in prior art FIGS. 1A and 1B, which respectfully show the use of such protective diodes in an N channel structure (FIG. 1A) and a P channel structure (FIG. 1B). In FIG. 1A, the gate oxide in N channel MOS structure 2, which may be formed in a P well, is protected by electrically connecting gate electrode 4 to one electrode of a reverse biased diode 6 having its other electrode electrically coupled to the P well. Similarly, as illustrated in FIG. 1B, the gate oxide in P channel MOS structure 12, which may be formed in a N well, is protected by electrically connecting gate electrode 14 to one electrode of a reverse biased diode 16 having its other electrode electrically coupled to the N well. Such use of diode protection devices to inhibit plasma charging damage to gate oxide is discussed by Shin, Ma, and Hu in an article entitled "Impact of Plasma Charging Damage and Diode Protection on Scaled Thin Oxide", published in IDEM 93 at pages 467-470.
While the use of such a diode or diodes will, from an electrical standpoint, operate to reduce or eliminate the problem of gate oxide charging and/or degradation, its physical implementation has resulted in geographical problems with regard to the location of the diode on the semiconductor substrate. Since the problem was created by the desire to further reduce the scale of devices and interconnects on the substrate, the need to, in turn, provide an additional diode for each MOS device, and to provide the geographical space laterally on the substrate for such a diode is self-defeating of the scaling down of the structure.
Prior art FIG. 2 illustrates this space problem. In FIG. 2, the MOS devices are respectively formed within islands 20 and 30 on an underlying semiconductor substrate (not shown), with polysilicon gate electrodes 22 and 24 forming MOS structures with source regions 26a and 26b and common drain region 28 of island 20; and polysilicon gate electrodes 32 and 34 forming MOS structures with source regions 36a and 36b and common drain region 38 of island 30. For each gate electrode, a diode is also formed in the underlying semiconductor substrate spaced from the corresponding gate electrode and electrically isolated therefrom by field oxide 40. Thus, diode 42 is spaced from gate electrode 22, diode 44 from gate electrode 24, diode 46 from gate electrode 32 and diode 48 from gate electrode 34.
In each instance, one electrode of diodes 42-48 is electrically wired, respectively, to the respective nearby gate electrode through one of the subsequently formed overlying metallization layers. Such a wiring of a diode or resistor to a gate electrode through metallization layers is shown, for example, in Lukaszek U.S. Pat. No. 5,315,145. It will be readily apparent that while such a solution may be electrically satisfactory, the addition of such diodes to the illustrated integrated circuit structure of FIG. 2 spaced laterally from the MOS devices results in the use of an unacceptable additional amount of lateral space on the surface of the substrate.
It would, therefore, be desirable to provide the protection of such a diode electrically connected between a gate electrode and the underlying substrate without, however, the physical use of additional lateral space on the substrate for the location of such a protective diode.